1. Field of the Invention
The invention relates to an integrated memory module having a self-test circuit, to a test system and also to a method for testing integrated memory modules.
2. Description of the Related Art
In order to check integrated memory modules with regard to their functionality after the production process, they are tested. For this purpose, the integrated memory modules are connected to a tester device and a test operation is started, during which each of the memory cells of the integrated memory module is checked with regard to predetermined specifications.
The memory module is tested by data being written in and subsequently read out again, defect data being generated from a comparison between data written in and data stored in the relevant memory cell, which defect data specify whether the memory cell is defective or functions correctly. The generation of the data for testing the memory module can be effected by a self-test circuit which also determines the defect data.
Said defect data have to be transferred from each of the memory modules to be tested to the testing test device. This is time-consuming and considerably restricts the throughput of integrated memory modules.
The defect data determined serve to determine a repair solution which makes it possible to replace defective memory areas in the integrated memory module by redundantly provided memory areas which are likewise present in the integrated memory module. However, since a defective memory cell is not replaced by a redundant memory cell, but rather by a redundant memory area, it suffices, for the determination of the repair solution, to obtain only a defect address of the memory area in which one or a plurality of defective memory cells are situated. This may be done for example as early as in the self-test circuit provided in the integrated memory module, so that the defect data to be transferred to the tester device are already compressed. Since no information required for determining the repair solution is lost as a result, the term redundancy-conforming compression is used.
Despite compression, the time taken to transfer the defect data is considerable and the throughput when testing integrated memory modules on a tester device is thus restricted.